1. Field of the Invention
This invention relates to a masterslice integrated circuit device, and more particularly to a structure of an improved degree of integration.
2. Description of Related Art
Recently, a requirement to produce integrated circuit devices of different functions with a low manufacturing cost and a short manufacturing time has been enhanced. In response to this requirement, a masterslice technique is a most useful one in which basic cells including circuit elements such as transistors, diodes and resistors are commonly fabricated by impurity diffusion process, and in some cases, all contact holes for leading-out electrodes are commonly formed, in advance, on a master semiconductor substrate, and thereafter, at a wiring process, personalization wirings are made utilizing different masks to connect the elements to each other to obtain a desired function for a specific application. The masterslice techniques are described, for example, in U.S. Pat. Nos. 4,500,906, 4,523,106, 4,661,815, 4,737,836, 4,771,327 and 4,825,276.
FIG. 1 is a plan view to show a prior art IC device of masterslice technique and FIG. 2 is a cross-sectional view along the line B--B' in FIG. 1 as viewed in the direction of arrows. A semiconductor substrate 1 is composed of a P-type silicon body 1, an N-type epitaxial layer which forms a plurality of collector regions 13 formed on the silicon body 1, N.sup.+ -type buried layers 14 positioned between the collection regions 13 and the silicon body 1, a P-type isolation region 12 having a grid-like plan shape and surrounding every collector region 13, P-type base regions 15 formed on the respective N-type collector regions, N.sup.+ -type emitter regions 17 formed on the respective P-type base regions, N.sup.+ -type collector contact regions 16 formed in the respective N-type collector regions, and an insulating film 18 including a thick field insulating layer at least on the P-type isolation region 12. The N-type collector region 13 defines every basic cell region so that the basic cell is constituted of one bipolar transistor, and a wiring forming region 22 or a channel region for forming wirings, of a grid-like plan shape is provided on the insulating film 18 just above the P-type isolation region 12. Contact holes 4 are formed in the insulating film 18, and aluminum electrodes 5 are connected to the emitter and collector contact regions 17, 16 via polycrystalline silicon electrodes 3 through the contact holes 4, and to the base regions 15 directly through contact holes 4. After necessary impurity diffusion process steps for forming the base regions, the emitter regions and the collector contact regions, the isolation region, etc. and the process steps for forming the above-mentioned electrodes have been performed, the semiconductor substrate in wafer state may be stored as a masterslice substrate. When functions to be provided in the IC device are determined, personalization wirings 6 of aluminum are formed to connected selected transistors to each other to form a predetermined circuit having the desirable functions. In FIGS. 1 and 2, the transistors 2a are elements (basic cells) which are used to form a predetermined circuit while the transistors 2b are elements (basic cells) of not necessary to be used here. Therefore, the aluminum electrodes 5 of the elements 2b which are not in use are not connected to other elements, whereas the aluminum electrodes 5 of the elements 2a which are in use are connected to other elements via aluminum wirings 6. The aluminum wirings 6 are formed on wiring forming regions 22 provided between elements, that is, between the basic cells 20.
The aforementioned prior art IC device of masterslice technique has, however, a problem in that a certain space (width) W.sub.1 should be given between adjacent elements (basic cells) in order to secure the formation of the personalization wirings 6, although a sufficient isolation itself between collector regions 13 can be obtained even if the P-type isolation regions 12 would be narrower. The prior art IC device, therefore, cannot be integrated beyond a certain degree and poses a difficulty in increasing the integration.